Periodic signals are used in a variety of electronic devices. One type of periodic signal is a clock signal that can be used to establish the timing of a signal or the timing at which an operation is performed on a signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock signal or data strobe signal. More specifically, read data signals are typically coupled from a memory device in synchronism with either a clock signal or a read data strobe signal that may be synchronous with a clock signal. The read data strobe signal is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a clock signal or a write data strobe signal that may also be synchronous with a clock signal. Other signals generated in electronic devices, such as memory devices or memory controllers, are often synchronized or triggered by an internal clock signal. For example a clock signal may be used in a memory device for latching write data and/or outputting read data. The clock signal is typically generated in the memory device from an internal clock signal using a delay-lock loop.
One of the advantages of using a delay lock loop to generate an internal clock signal in an integrated circuit is that various delays in an integrated circuit can be modeled by delay model circuits and used in the feedback path of a delay lock loop to compensate for such delays. For example, the delay in coupling a clock signal through a clock tree to a read data latch can be modeled by a model delay in the feedback path of a delay lock loop that generates the clock signal. As a result, read data may be latched and thus output from the memory device substantially in synchronism with a clock signal despite a propagation delay of a clock signal through the clock tree.
While various techniques such as a delay lock loop containing a model delay may alleviate to some extent problems resulting from propagation delays in integrated circuits, the problems of signal propagation delays may become more severe in a semiconductor device using multiple semiconductor die, such as where the multiple die are stacked. More specifically, even if propagation delays can be compensated for in each die, there may still be propagation delays in coupling signals between each die and external electrical connectors (e.g., terminals) of the integrated circuit device. With reference to FIG. 1, a semiconductor device 10 may include 4 semiconductor die 12, 14, 16, and 18, some of which may be identical to each other or different from each other. The die 12-18 may be mounted on a surface 20 of a substrate 24, and external terminals in the form of a ball grid array 28 may be mounted on an opposed surface 30 of the substrate 24. One of the balls 32 of the ball grid array 28 may receive a clock signal (CLK”), and a plurality of other balls 34 (only one is shown) may receive and transmit data signals. Individual balls of the array ball grid array 28 may be coupled to the die 12-18 through respective internal balls 38 positioned against each surface of the die 12-18 between adjacent die or between the die 12 and the substrate 24. Signals may be coupled from one surface of the die 12-18 to an opposite surface by internal electrical connectors such as through silicon vias (“tsv”) 40.
FIG. 2 shows a semiconductor device 52 that also includes the stacked die 12-18. The semiconductor device 52 may be substantially similar to the semiconductor device 10 of FIG. 1. Therefore, in the interest of brevity and clarity, identical reference numerals will be used to identify identical components. The device 52 differs from the device 10 by using bond wires 62, 64, 66, 68 as internal electrical connectors to couple all or some signals from the substrate 24 to the die 12-18. However, the device 52 may also use the internal balls 38 to couple signals between the die 12-18.
Regardless of whether the signal coupling technique shown in FIG. 1 or FIG. 2 is used or some other technique is used, the propagation delay in coupling signals between the external electrical connectors 28 and the die 12-18 may differ from die-to-die. For example, the CLK signal will be received by the die 12-18 with increasingly larger delays from the die 12 to the die 18. As a result, for example, read data may be output from the die 12-18 at increasing distances from the electrical connectors 28. Moreover, the propagation delay in coupling the read data from each of the die 12-18 to the electrical connectors 28 may increase from the die 12 to the die 18. Insofar as the read data from the devices 10, 50 may be latched by an external device in synchronism with the CLK signal or some other signal, the “data eye” during which the read data is valid may become increasingly later for die 12-18 farther away from the electrical connectors 28. More importantly, the overlap in the respective data eyes from the die 12-18 may set the overall data eye for the device 12-18 during which read data from the devices 10, 50 is valid regardless of which die originated the read data. The size of the data eye may therefore become smaller as the common data valid time overlaps in the respective data eyes from the die 12-18 become smaller. A smaller data eye may make it more difficult for an external device to correctly latch read data from the devices 10, 50. This skewed data eye problem gets worse when duty cycle distortion is present. Similar types of problems may exist for other types of signals, such as write data signals.
The problems resulting from differences in the connections between the electrical connectors 28 and each of the die 12-18 may also result in problems other than signal propagation problems, such as output slew rate skew, ZQ calibration termination impedance mismatch, etc. For example, the longer signal paths between the electrical connectors 28 and the die farther away from the electrical connectors 28 may increase the resistance between the electrical connectors 28 and the die 12-18 farther away from the electrical connectors. As a result, the “drive strength” of signal transmitters on the die 12-18 may become increasing less away from the electrical connectors 28. The increased resistance between the electrical connectors 28 and the die 12-18 farther away from the electrical connectors 28 may also cause the termination impedance of the balls of aball grid array, for example, to be larger for die 12-18 farther away from the ball grid array.